1. Field of Invention
The present invention relates to a source driver of a display panel. More particularly, the present invention relates to a source driver of a display panel which has reduced circuit wiring, and timing control method thereof.
2. Description of Related Art
Recently, the flat panel displays including thin film transistor liquid crystal displays (TFT-LCD), low temperature ploy-silicon (LPTS) liquid crystal displays, and organic light-emitting displays (OLED) have continued to progress. Wherein the displaying portion of a flat panel display is composed of pixel arrays. Generally, the pixel array is a determinant matrix which is controlled by a driver to drive the corresponding pixels according to dots of image data and displays the designated color at the designated time. FIG. 1 is a block diagram illustrating a conventional source driver. Referring to FIG. 1, the source driver 100 includes a shift register 102, a line latch 104, a level shifter 106, a digital to analog converter (DAC) 108, an output buffer 110, and a gray scale voltage generator 112. Signals including start signal, shift signal, clock signal, polarity signal, and control signal are used in driving operation of source driver 100. Wherein, after a data signal input 101 is transmitted into line latch 104, the data signal will be sequentially transferred through the components in said source driver according to start signal, shift signal, clock signal, as shown in FIG. 1. The DAC 108 receives the polarity signal and simultaneously the control signal is received by the DAC 108 and the line latch 104, the gray scale voltage generator 112 outputs the desired voltages. Finally, the analog voltages are outputted as driving voltages to the transistors of the display pixels through the output channels (Y1˜Y384 in FIG. 1) respectively after passing through output buffer 110.
To provide a display panel having high resolution display performance, a Gamma voltage generator within the source driver must be able to provide more different voltages for data transmitting condition of more bits. Therefore, the circuit wiring needed within a Gamma voltage generator is of a large number and takes up a lot of space within the source driver. FIGS. 2A and 2B illustrate a representative diagram and the block diagram of the circuit of a conventional Gamma voltage generator, respectively. Referring to FIGS. 2A and 2B, a conventional Gamma voltage generator generates voltages by inputting a plurality of reference voltages Vgamma x (Vgamma 1˜Vgamma m as shown in FIG. 2) from the outside of the source driver, and then obtaining a plurality of desired gray-scale voltages, as the N number of gray-scale voltages (0th Gray Scale˜Nth Gray Scale shown in FIG. 2) which are provided for the source driver, by performing voltage-dividing using a R-Ladder circuit composed of a plurality of resistors connected in series. FIG. 2B illustrates the circuit block diagram of the Gamma voltage generator in FIG. 2A. As described above, the Gamma voltage generator 200 receives external reference voltages Vgamma to generate desired N number of gray-scale voltages, and wires of those gray scale voltages are electrically connected to DACs. Therefore, the number of different voltages required depends on the gray-scale voltages needed for the displaying resolution of a specific display panel. To be brief, multiple Gamma voltages are obtained by utilizing multiple reference voltages and accompanying R-ladder circuit. However, as the requirement for more different Gamma voltages increases, the space taken by circuit wiring would continue to expand.
Accordingly, to overcome the disadvantage that circuit wiring occupies too much space in the conventional source driver, the present invention provides a source driver which uses the combination of a voltage generator and voltage switch set, capable of effectively reducing the number of wires. In addition, the present invention also provides a timing control method which is used for driving data signals of the source driver.